![]() Remember that you may reuse hardware from earlier labs (such as the ALU, multiplexers, registers, sign-extension hardware modules, register file, etc.) wherever possible. Datapath Design Refer to Figure for the hardware modules you need to set up your datapath. If you find any errors, debug your circuit and correct the errors. Also verify that PCEn performs correctly. Visually inspect the states and outputs to verify that they match your expectations from Table 4. Such testbench should test each of the instructions that the processor should support (add, sub, and, or, slt, lw, sw, beq, addi, and j), and both taken and nontaken branches. It would be a good idea to have a controllertest testbench for the controller module. The controller header is given showing its inputs and outputs. ![]() Also include any additional logic needed to compute PCEn from the internal signals, Branch, and Zero. ![]() Design your controller using an FSM for the Main Decoder and combinational logic for the ALU Decoder. The state transition diagram is also given at the end of this handout. The control unit should support the instructions from Figure 7.42 in the text. On reset, the control unit should start at State 0. The Main Decoder, maindec, should take the Opcode input and produce the outputs described in Table 4. Memory (mem) 3Ĥ Control Unit Design The control unit consists of two modules, the Main Decoder and the ALU Decoder. Datapath Note that and Branch are internal signals (wires) within the controller. Reset Reset Op PCEn Funct Zero MemtoReg MemtoReg ALUSrcB ALUControl PCSrc ALUSrcB ReadData ALUControl Op PCSrc Funct PCEn Zero Table. Multicycle Processor 2ģ Unit Overview The three units have the following inputs and outputs. The memory is essentially identical to the data memory from Lab 4 and is provided for you.Ģ MemtoReg control 3:26 5:0 Control Unit Op Funct Branch PCSrc :0 ALUControl 2:0 ALUSrcB :0 PCEn PC' PC 0 EN Adr A mem RD Instr / Data Memory WD WE Instr EN Data 25:2 20:6 20:6 5: 0 0 A A2 A3 WD3 WE3 Register File RD RD2 A B 3: << SrcA SrcB ALU Zero ALUResult ALUOut PCJump <<2 27: :0 Sign Extend ImmExt 25:0 (jump) datapath Figure. In this lab you have to design both the cotroller and the datapath. The controller module should in turn instantiate the main decoder module (maindec) and the ALU decoder module (aludec). The mips module instantiates both the datapath and control unit (called the controller module). Start with the mipsmulti.v file that is given to you. Overall Design Now you will begin the hardware implementation of your multicycle processor. It takes much longer to debug an erroneous circuit than to design it correctly the first time. The first two rows are filled in as examples. Give the FSM control word in hexadecimal for each state. Complete the output table of the Main Decoder in Table 4. This state transition diagram is shown in Figure 7.42 in the book (also reprinted here as Figure 2). Generating Control Signals Before you begin developing the hardware for your MIPS multicycle processor, you ll need to determine the correct control signals for each state in the multicycle processor s state transition diagram. The controller unit also includes the gates needed to produce the write enable signal, PCEn, for the PC register. Also note that the controller unit comprises both the Main Decoder that takes OP 5:0 as inputs and the ALU Decoder that takes as inputs ALUOp :0 and the Funct 5:0 code from the 6 least significant bits of the instruction. Note that the mem unit contains the shared memory used to hold both data and instructions. The multicycle processor is divided into three units: the controller, datapath, and mem (memory) units. It should handle the following instructions: add, sub, and, or, slt, lw, sw, beq, addi, and j. Your multicycle processor should match the design from the text, which is reprinted in Figure for your convenience. You may reuse any of your hardware (Verilog modules) from previous labs. 1 Introduction Lab #5: MIPS Multi-Cycle Processor In this lab you will design and build your own multicycle MIPS processor.
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